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Ordering number : ENN*6722
CMOS IC
LC868364A
8-Bit Single Chip Microcontroller with 64K-Byte ROM and 512-Byte RAM On Chip
Preliminary Overview
The LC868364A microcontroller is an 8-bit single chip microcontroller with the following on-chip functional blocks: - CPU: Operable at a minimum bus cycle time of 0.5s - On-chip ROM capacity: 64K bytes - On-chip RAM capacity: 512 bytes - Dot-matrix liquid crystal display (LCD) automatic display controller/driver - External memory - 16-bit timer/counter (or two 8-bit timers) - 16-bit timer/PWM (or two 8-bit timers) - 13-source 9-vectored interrupt function All of the above functions are fabricated on a single chip.
Features
(1) Read Only Memory (ROM): (2) Random Access Memory (RAM): 65,280 x 8 bits 512 x 8 bits (calculation area) 128 x 8 bits (display area)
Ver.1.03 21700
91400 RM (IM) HO No.6722-1/29
LC868364A (3) Bus Cycle Time/Instruction Cycle Time
Bus cycle time 0.5s 0.75s 1.0s 7.5s 3.8s 183s 93s Instruction Cycle Time 1s 1.5s 2s 15.0s 7.5s 366s 183s System Clock Oscillation Ceramic (CF) Ceramic (CF) Ceramic (CF) Internal RC (or external RC) Crystal (Xtal)
Oscillation Frequency
Voltage 3.3-6.5V 2.7-6.5V 2.4-6.5V 2.4-6.5V 2.2-6.5V
Other OCR7=0 OCR7=1 OCR7=1 OCR7=0 OCR7=1 OCR7=0 OCR7=1 OCR7=0 OCR7=1
12MHz 6MHz 4MHz 6MHz 3MHz 800kHz 32.768kHz
* Bus cycle time: ROM-read period
OCR7: Oscillation control register bit-7
(4) Ports - Input/output ports: 6 ports (48 terminals) I/O programmable in nibble units: I/O programmable for each bit individually: - Input port: 1 port (4 terminals) - LCD drive common output ports: - LCD drive segment output ports:
1 port (8 terminals) 5 ports (40 terminals) 32 terminals/16 terminals (switched by mask option) 32 terminals/48 terminals (switched by mask option)
(5) External Program Memory Access Function - Ports 1. Data input/output: 1 port (8 terminals) 2. Address output: 2 ports (16 terminals) 3. Bank address output: Use normal I/O ports as bank address output by program control. - External program memory access function External program memory space: 64K bytes Internal/external program can be switched by program. (at initial: internal program operation mode) Enabling/ disabling of switching from external program to internal program is provided. - External data memory access function By LDC instruction execution: External data memory space: 64K bytes (Use normal I/O ports as bank address output by program control.) 1. When internal program is operating: Access to the internal or external ROM data is selectable by program. 2. When external program is operating: Only the external ROM data can be accessed. (Only the external program memory space (64K bytes) can be referred.) - External RAM memory access function (Able to be used when internal program is executed) By LDX instruction/STX instruction execution: External RAM space: 64K bytes (Use normal I/O ports as bank address output by program control.) (When using the external RAM space in the external program operation mode, refer to the "LC868364 User's Manual" for details.) (6) LCD Automatic Display Controller/Common Driver/Segment Driver - Display duty: 1/32 duty, 1/16 duty - Display bias: 1/5, 1/7 bias - Graphic display A maximum of 1,024 dots capability (without external segment driver) 32 x 80 dots display capability per each segment driver (LC868920A) can be expanded, when 1/32 duty is selected. Note: If the display capability is expanded by the LC86920A when 1/16 duty is selected, only S1-S32 of the LC868364A can be used, and S33-S48 can not be used. (Refer to the LC868920A specification sheet.)
No.6722-2/29
LC868364A - LCD contrast LCD display contrast is changeable by program. - LCD power supply (max. 6V): externally boosted output terminal (assigned at P40 terminal, The terminal function is selectable by program.) - LCD driver Following two kinds of combination can be switched by mask option.
Segment Output Terminals 1 2 32 48 Common Output Terminals 32 16
- LCD clock: Select the crystal oscillation circuit output (in order to reduce the current consumption when LCD is on) - LCD drive frequency: 102Hz (32.768kHz crystal oscillation) (7) Serial Interface - Synchronous 8-bit serial interface x 2 channels (built-in 8-bit baud rate generator) (8) Timer - Timer 0 (T0L, T0H) 16-bit timer/counter 2-bit prescaler + 8-bit programmable prescaler Mode 0: Two 8-bit timers with programmable prescaler Mode 1: 8-bit timer with programmable prescaler + 8-bit counter Mode 2: 16-bit timer with programmable prescaler Mode 3: 16-bit counter - Timer 1 (T1L, T1H) 16-bit timer/PWM Mode 0: Two 8-bit timers Mode 1: 8-bit timer + 8-bit PWM Mode 2: 16-bit timer Mode 3: Variable bit PWM (9-16 bits) - Base Timer Generates an overflow every 500ms for a clock application. (using a 32.768kHz crystal oscillation for the base timer clock.) Clock for the base timer is selectable from 32.768kHz crystal oscillation, system clock or programmable prescaler output of Timer 0. (9) Buzzer Output - Built-in 4kHz and 2kHz buzzer generation function (10) Remote Receiver Circuit (shares with P73/INT3/T0IN terminal) - Noise rejection function - Polarity switch function (11) Watchdog Timer - External RC circuit is required (connected to P70/INT0 terminal) - Interrupt or system reset is activated when the timer overflows.
No.6722-3/29
LC868364A (12) Interrupt - 13-source and 9-vectored interrupt function: 1. External interrupt INT0 (including watchdog timer) 2. External interrupt INT1 3. External interrupt INT2, timer/counter T0L (lower 8 bits of Timer 0) 4. External interrupt INT3, base timer 5. Timer/counter T0H (upper 8 bits of Timer 0) 6. Timer T1L (lower 8 bits of Timer 1), Timer T1H (upper 8 bits of Timer 1) 7. Serial interface SIO0 8. Serial interface SIO1 9. Port 0 or Port 3 - Built-in Interrupt Priority Control Three interrupt priorities are supported (low, high and highest) and multi-level nesting is possible. Low or high priority can be assigned to the 11 interrupt sources, from the external interrupt INT2, Timer/Counter T0L (Timer 0, lower 8 bits) to Port 0 or Port 3. For the external interrupt INT0 and INT1, low or highest priority can be set regardless of the interrupt priority register. (13) Sub-routine Stack Level - A maximum of 128 levels: (sets stack inside RAM) (14) Multiplication/Division Instruction - 16 bits x 8-bit (7 instruction-cycle-times) - 16 bits / 8-bit (7 instruction-cycle-times) (15) Three Types of Oscillation Circuit - Built-in/external RC oscillation circuit used for the system clock - CF oscillation circuit used for the system clock - Xtal oscillation circuit used for the clock, system clock and LCD * Crystal oscillation clock is also used as LCD display base clock. The current consumption of this microcontroller becomes smaller than the Sanyo's previous microcontrollers by this configuration. Built-in/external RC oscillation circuit: switched by mask option (16) Standby Function - HALT mode In this operation mode, the program execution is stopped. The mode can be released by a system reset or an interrupt request. - HOLD mode The HOLD mode is used to stop the oscillations; CF, RC, and Xtal oscillations. This mode can be released by the following conditions: * System reset * Feed the selected level to INT0 or INT1 terminals. * Feed "L" level to the Port 0 or Port 3. (17) Operating Supply Voltage Range - VDD=2.4 to 6.5V - VLCD=2.5 to 6.5V (LCD power supply) (18) Shipping Form - Chip (19) Development Tool - Evaluation (EVA) chip: - Emulator:
LC868099 EVA86000(main) + ECB868300 (evaluation board)
No.6722-4/29
LC868364A
Pad Assignment
- Chip size (X x Y): - Thickness of chip : - Pad size - Pad pitch : :
(Display duty: 1/32 duty) 5.38mm x 4.84mm 480m 100m x 100m 120m
SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 COM32 COM31 COM30 COM29 COM28 COM27 COM26 COM25 COM24 COM23 COM22 COM21 COM20 COM19 COM18 COM17 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1
35
SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 V1 V2 V3 V4 V5 VLCD RC1 RC2 30 25 20 15 10 5 2 1 135
40
130 45
125 50
120 55
115 60
110 65
105 70 103 75 80 85 90 95 100 102
VDD CF2 CF1 VSS XT2 XT1 RES EROE ADLC P27 P26 P25 P24 P23 P22 P21 P20 P07 P06 P05 P04 P03 P02 P01 P00 P37 P36 P35 P34 P33 P32 P31 P30 VDD
VSS P40 P41 P42 P43 P44 P45 P46 P47 P70 P71 P72 P73 P10 P11 P12 P13 P14 P15 P16 P17 P57 P56 P55 P54 P53 P52 P51 P50
No.6722-5/29
LC868364A
Pad Assignment
- Chip size (X x Y): - Thickness of chip : - Pad size : - Pad pitch :
(Display duty: 1/16 duty) 5.38mm x 4.84mm 480m 100m x 100m 120m
SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1
35
SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 V1 V2 V3 V4 V5 VLCD RC1 RC2 30 25 20 15 10 5 2 1 135
40
VDD CF2 CF1 VSS XT2 XT1 RES EROE ADLC P27 P26 P25 P24 P23 P22 P21 P20 P07 P06 P05 P04 P03 P02 P01 P00 P37 P36 P35 P34 P33 P32 P31 P30 VDD
130 45
125 50
120 55
115 60
110 65
105 70 103
VSS P40 P41 P42 P43 P44 P45 P46 P47 P70 P71 P72 P73 P10 P11 P12 P13 P14 P15 P16 P17 P57 P56 P55 P54 P53 P52 P51 P50
No.6722-6/29
LC868364A
Application Circuit
(Display duty: 1/32 duty)
LCD Panel 32 32 COM 32 x 112 dots
32
80
SEGMENT DRIVER 80 SEG LC868920A
Mask ROM 4M Byte DATA
OE ADDRESS
COM1-32
SEG1-32 DATA EROE Control signal
Power supply for LCD LC868364A KEY MATRIX 8-bit single chip microcomputer 8x8
No.6722-7/29
LC868364A
Pad Name and Coordinates Table
Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 Name VDD RC2 RC1 VLCD V5 V4 V3 V2 V1 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 COM32 COM31 COM30 COM29 COM28 Coordinates Xm 2178 1967 1836 1663 1543 1423 1303 1183 1063 942 822 702 582 462 342 223 103 -17 -137 -257 -377 -497 -617 -737 -857 -977 -1097 -1217 -1337 -1457 -1577 -1697 -1817 -1937 -2057 -2177 -2179 -2179 -2179 -2179 -2179 -2179 -2179 -2179 -2179 -2179 Ym 2330 2449 2449 2449 2449 2449 2449 2449 2449 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2172 2052 1932 1812 1692 1572 1452 1332 1212 1092 Pad No. 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92
(Display duty: 1/32 duty)
Coordinates Xm -2179 -2179 -2179 -2179 -2179 -2179 -2179 -2179 -2179 -2179 -2179 -2179 -2179 -2179 -2179 -2179 -2179 -2179 -2179 -2179 -2179 -2179 -2179 -2179 -2179 -2179 -2179 -1673 -1543 -1413 -1283 -1153 -1023 -893 -763 -633 -503 -373 -243 -113 17 147 277 407 537 667 Ym 972 852 732 612 492 372 252 132 12 -108 -228 -348 -468 -588 -708 -828 -948 -1068 -1188 -1308 -1428 -1548 -1668 -1788 -1908 -2028 -2148 -2442 -2442 -2442 -2442 -2442 -2442 -2442 -2442 -2442 -2442 -2442 -2442 -2442 -2442 -2442 -2442 -2442 -2442 -2442 Pad No. 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 Coordinates Xm 797 927 1057 1187 1317 1447 1577 1707 1837 1967 2178 2178 2178 2178 2178 2178 2178 2178 2178 2178 2178 2178 2178 2178 2178 2178 2178 2178 2178 2178 2178 2178 2178 2178 2178 2178 2178 2178 2178 2178 2178 2178 2178 Ym -2442 -2442 -2442 -2442 -2442 -2442 -2442 -2442 -2442 -2442 -2294 -2104 -1974 -1844 -1714 -1584 -1454 -1324 -1194 -1064 -934 -804 -674 -544 -414 -284 -154 -24 106 236 366 496 626 756 886 1216 1346 1476 1606 1736 1866 1996 2126
Name COM27 COM26 COM25 COM24 COM23 COM22 COM21 COM20 COM19 COM18 COM17 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 VSS P40 P41 P42 P43 P44 P45 P46 P47 P70 P71 P72 P73 P10 P11 P12 P13 P14 P15
Name P16 P17 P57 P56 P55 P54 P53 P52 P51 P50 VDD P30 P31 P32 P33 P34 P35 P36 P37 P00 P01 P02 P03 P04 P05 P06 P07 P20 P21 P22 P23 P24 P25 P26 P27 ADLC EROE RES XT1 XT2 VSS CF1 CF2
The values (X, Y) indicate the coordinates of each pad center with the center of the chip as the origin.
No.6722-8/29
LC868364A
Pad Name and Coordinates Table
Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 Name VDD RC2 RC1 VLCD V5 V4 V3 V2 V1 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 Coordinates Xm 2178 1967 1836 1663 1543 1423 1303 1183 1063 942 822 702 582 462 342 223 103 -17 -137 -257 -377 -497 -617 -737 -857 -977 -1097 -1217 -1337 -1457 -1577 -1697 -1817 -1937 -2057 -2177 -2179 -2179 -2179 -2179 -2179 -2179 -2179 -2179 -2179 -2179 Ym 2330 2449 2449 2449 2449 2449 2449 2449 2449 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2172 2052 1932 1812 1692 1572 1452 1332 1212 1092 Pad No. 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92
(Display duty: 1/16 duty)
Coordinates Xm -2179 -2179 -2179 -2179 -2179 -2179 -2179 -2179 -2179 -2179 -2179 -2179 -2179 -2179 -2179 -2179 -2179 -2179 -2179 -2179 -2179 -2179 -2179 -2179 -2179 -2179 -2179 -1673 -1543 -1413 -1283 -1153 -1023 -893 -763 -633 -503 -373 -243 -113 17 147 277 407 537 667 Ym 972 852 732 612 492 372 252 132 12 -108 -228 -348 -468 -588 -708 -828 -948 -1068 -1188 -1308 -1428 -1548 -1668 -1788 -1908 -2028 -2148 -2442 -2442 -2442 -2442 -2442 -2442 -2442 -2442 -2442 -2442 -2442 -2442 -2442 -2442 -2442 -2442 -2442 -2442 -2442 Pad No. 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 Coordinates Xm 797 927 1057 1187 1317 1447 1577 1707 1837 1967 2178 2178 2178 2178 2178 2178 2178 2178 2178 2178 2178 2178 2178 2178 2178 2178 2178 2178 2178 2178 2178 2178 2178 2178 2178 2178 2178 2178 2178 2178 2178 2178 2178 Ym -2442 -2442 -2442 -2442 -2442 -2442 -2442 -2442 -2442 -2442 -2294 -2104 -1974 -1844 -1714 -1584 -1454 -1324 -1194 -1064 -934 -804 -674 -544 -414 -284 -154 -24 106 236 366 496 626 756 886 1216 1346 1476 1606 1736 1866 1996 2126
Name SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 VSS P40 P41 P42 P43 P44 P45 P46 P47 P70 P71 P72 P73 P10 P11 P12 P13 P14 P15
Name P16 P17 P57 P56 P55 P54 P53 P52 P51 P50 VDD P30 P31 P32 P33 P34 P35 P36 P37 P00 P01 P02 P03 P04 P05 P06 P07 P20 P21 P22 P23 P24 P25 P26 P27 ADLC EROE RES XT1 XT2 VSS CF1 CF2
The values (X, Y) indicate the coordinates of each pad center with the center of the chip as the origin.
No.6722-9/29
LC868364A
System Block Diagram
Interrupt Control
IR
PLA
Standby Control
ROM
CF RC X'tal
Clock Generator
PC
Base Timer
Base Timer
ACC
Port 1 SI/O 0 Port 7
B Register
C Register
Timer 0 ALU Timer 1 Port 2
Port 3
PSW
INT0-3 Noise Rejection Filter
Port 4
RAR
LCD Display Controller XRAM
Port 5
RAM
Stack Pointer
LCD Driver
Port 0
Port 0
Watchdog Timer
No.6722-10/29
LC868364A
Pad Description
Name VSS VDD VLCD V1 to V5 Port0 P00 to P07 No. 74,133 1,103 4 9-5 I/O I/O Function Description Power terminal (-) Power terminal (+) Power terminal (+) for LCD driver (for bleeder resistor) Voltage supply terminals to LCD drivers ! 8-bit input/output port ! Data direction programmable in nibble units ! External memory mode 1. EXT register bit 2=0 Address output of lower 8 bits, input/output of data 2. EXT register bit 2=1 ! Input/output of data ! Input for key interrupt (P30INT=0) (Note 2) ! 8-bit input/output port ! Data direction programmable for each bit individually ! Other functions P10 SIO0 data output P11 SIO0 data input, bus input/output P12 SIO0 clock input/output P13 SIO1 data output P14 SIO1 data input, bus input/output P15 SIO1 clock input/output P16 Buzzer output P17 Timer 1 output (PWM output) ! 8-bit input/output port ! Input/output can be specified in a bit ! External memory mode Address output of upper 8 bits ! 8-bit input/output port ! Data direction programmable for each bit individually ! External memory mode 1. EXT register bit 2=0: input/output port 2. EXT register bit 2=1:
address output of lower 8 bits for external memory
Option ! Pull-up resistor: provided/not provided ! Output form: CMOS/N-ch open drain (Note 1)
112-119
Port1 P10 to P17 87-94
I/O
! Output form: CMOS/N-ch open drain (Note 1)
Port2 P20 to P27 Port3 P30 to P37 104-111 120-127
I/O
! Output form: CMOS/N-ch open drain (Note 1) ! Pull-up resistor: provided/not provided ! Output form: CMOS/N-ch open drain (Note 1)
I/O
Port4 P40 to P47 75-82
I/O
! Input for key interrupt (P30INT=L) (Note 2) ! 8-bit input/output port ! Input/output can be specified each upper 2 bits and lower 6 bits ! Other functions P40 Externally boosted clock 2KOUT P41 Shift clock CL2 System clock for expansion P42 LCDP2
driver
! Pull-up resistor: provided/not provided ! Output form: CMOS/N-ch open drain (Note 1)
P43 P44 P45 P46 P47
Alternate signal General output port General output port Read signal Write signal
M P44 P45 RD WR
(P40-P43: LCD expansion signal, P46, P47: External RAM access signal)
No.6722-11/29
LC868364A
Name Port5 P50 to P57 No. I/O I/O Function Description 8-bit input/output port Data direction programmable for each bit individually Option Pull-up resistor: provided/not provided Output form: CMOS/N-ch open drain (Note 1) Pull-up resistor: provided/not provided
102-95
Port7 P70 to P73 83-86
I
4-bit input port Other functions P70 INT0 input/HOLD release/N-ch Tr. output for watchdog timer P71 INT1 input/HOLD release input P72 INT2 input/Timer 0 event input P73 INT3 input with noise filter/Timer 0 event input Interrupt detection style, vector address
Rising Falling INT0 INT1 INT2 INT3 Yes Yes Yes Yes Yes Yes Yes Yes Rising/ H level L level Vector Falling No Yes Yes 03H No Yes Yes 0BH Yes No No 13H Yes No No 1BH
C1 to C32 (Note 3) S1 to S32 RES ADLC
EROE XT1
73-42 10-41 130 128 129 131 132 134 135 3
O O I O O I O I O I
LCD output terminals for common LCD output terminals for segment Reset Address control signal for external memory Enable signal of external ROM output Input terminal for 32.768kHz Xtal When not in use, connect to VDD. Output terminal for 32.768kHz Xtal When not in use, leave open circuit. Input terminal for ceramic resonator When not in use, connect to VDD. Output terminal for ceramic resonator When not in use, leave open circuit. Input terminal for RC oscillation (when external RC oscillation is used) Put a resistor between RC1 and RC2, and a capacitor between RC1 and VSS externally. Leave open when internal RC oscillation is used. Output terminal for RC oscillation (when external RC oscillation is used) Put a resistor between RC1 and RC2 externally. Leave open when internal RC oscillation is used.
Segment output/ common output Internal/external
XT2 CF1 CF2 RC1
RC2
2
O
Internal/external
(Note 1) Nch-OD: N-channel open-drain output (Note 2) P30INT: Bit 0 of Port 3 interrupt control register (P3INT). * Port options can be specified for each bit individually. (Note 3) C1-C32 are the terminal names when 1/32 duty is selected. C1-C16 and S48-S33 are the terminal names when 1/16 duty is selected. Refer to "Pad Assignment" in pages 5-6.
* A state of port at initial
Pin Name Port 0, 7 Ports 1, 2 Ports 3, 5 Port 4 Name C1 to C32 S1 to S32 Input/output Mode Input Input Input Output Level VSS (display OFF) VSS (display OFF) Style of pull-up resistors when pull-up option is enabled Fixed pull-up resistor provided Programmable pull-up resistor OFF Programmable pull-up resistor ON
No.6722-12/29
LC868364A 1. Absolute Maximum Ratings at VSS=0V and Ta=25C
Parameter Supply Voltage Input Voltage Symbol Pins Conditions Ratings unit typ. max. V +7.0 VDD+0.3 +7.0 VLCD+0.3 VDD+0.3 VDD+0.3
VDD[V]
Output Voltage
VDDMAX VDD VI(1) *Ports 71,72,73 * RES VI(2) VLCD VO(1) *C1 to C32 *S1 to S32 VO(2) ADLC, EROE VIO(1) *Ports 0,1,2,3,4,5 *Port 70 *ADLC *Ports 0,1,2,3,4,5 *ADLC, EROE *Ports 0,2,3 *C1-C32,S1-S32 *ADLC, EROE Ports 1, 4, 5 *Ports 0,1,2,3,4,5 *ADLC, EROE Port 70 Port 0 *Port 2 *ADLC, EROE Port 3 Ports 1, 5 Port 4 Port 70 C1-C32,S1-S32
min. -0.3 -0.3 -0.3 -0.3 -0.3 -0.3
Input/output Voltage
High Level Output Current
Peak Output Current Total Output Current Peak Output Current Total Output Current
IOPH(1) IOAH(1)
*CMOS output *For each pin Total of all pins
-4
mA
-25
Low Level Output Current
IOAH(2) IOPL(1) IOPL(2) IOAL(1) IOAL(2) IOAL(3) IOAL(4) IOAL(5) IOAL(6) IOAL(7) Topr
Total of all pins For each pin For each pin Total of all pins Total of all pins Total of all pins Total of all pins Total of all pins Total of all pins Total of all pins
-25 20 15 40 40 40 40 40 15 30 +70
Operating Temperature Range Storage Temperature Range
-30
-
C
Tstg
-55
-
+125
Notes: The specification above indicates the state when a die is mounted in a package, SQFC144. However, we ship this product in a chip, not in a package. Make sure that the operational characteristics may vary by the user's package techniques.
No.6722-13/29
LC868364A 2. Recommended Operating Range at Ta=-30C to +70C, VSS=0V
Parameter Operating Supply Voltage Range Hold Voltage Symbol VDD(1) VDD(2) VDD(3) VHD VDD Pins Conditions
0.98s tCYC 400s 1.49s tCYC 400s 1.98s tCYC 400s
VDD[V]
min. 3.3 2.7 2.4 2.0
Ratings typ.
max. 6.5 6.5 6.5 6.5
unit
V
VDD
RAM and register data are kept in HOLD mode. 2.4-2.5 2.5-3.0 3.0-6.5 2.4-6.5 2.4-6.5
LCD Display Voltage Input High Voltage
VLCD
VLCD
VIH(1) VIH(2)
Port 0
(Schmitt)
Output disable Output disable
VIH(3)
VIH(4) Input Low Voltage VIL(1) VIL(2)
VIL(3)
VIL(4) Operation Cycle Time Oscillation Frequency Range (Note 1) tCYC
*Ports 1,2,3,4,5 *Ports 72,73 (Schmitt) *Port 70 for Port input/interrupt *Port 71 * RES (Schmitt) Port 70 for watchdog timer Port 0 (Schmitt) *Ports 1,2,3,4,5 *Ports 72,73 (Schmitt) *Port 70 Port input/interrupt *Port 71 * RES Port 70 for watchdog timer
2.5 VDD VDD 0.4VDD +0.9 0.7VDD
6.5 6.5 6.5 VDD VDD
Output N-channel Tr. OFF
2.4-6.5
0.7VDD
VDD
Output N-channel Tr. OFF Output disable Output disable
2.4-6.5 2.4-6.5 2.4-6.5
0.9VDD VSS VSS
VDD 0.2VDD 0.3VDD
Output N-channel Tr. OFF
2.4-6.5
VSS
0.3VDD
Output N-channel Tr. OFF
2.4-6.5 3.3-6.5 2.7-6.5 2.4-6.5 2.4-6.5
VSS 0.98 1.49 1.98 0.3
FmRC
RC1, RC2
*External RC oscillation *Refer to figure 3
0.8VDD -1.0 400 s 400 400 3 MHz
(Note 1): Oscillation parameters are shown in "Recommended Oscillation Circuit and Characteristics" in page 20.
No.6722-14/29
LC868364A 3. Electrical Characteristics at Ta=-30C to +70C, VSS=0V
Parameter Input High Current Symbol IIH(1) Pins *Ports 1,2,3,4,5 *Port 0 without pull-up MOS Tr. Conditions *Output disable *Pull-up MOS Tr. OFF *VIN=VDD (including the offleak current of the output Tr.) *Output Nch Tr. OFF *VIN=VDD (including the offleak current of the output Tr.) VIN=VDD *Output disable *Pull-up MOS Tr. OFF *VIN=VSS (including the offleak current of the output Tr.) *Output Nch Tr. OFF *VIN=VSS (including the offleak current of the output Tr.) VIN=VSS IOH=-10mA IOH=-1mA IOH=-1.0mA IOH=-0.1mA Ratings typ. unit A
VDD[V] 2.5-6.5
min.
max. 1
IIH(2)
Port 7 without pull-up MOS Tr.
2.5-6.5
1
IIH(3) Input Low Current IIL(1)
RES *Ports 1,2,3,4,5 *Port 0 without pull-up MOS Tr.
2.5-6.5 2.5-6.5 -1
1
IIL(2)
Port 7 without pull-up MOS Tr.
2.5-6.5
-1
IIL(3) Output High Voltage VOH(1) VOH(2) VOH(3) VOH(4)
Output Low Voltage
VOL(1) VOL(2) VOL(3) VOL(4) VOL(5) Rpu VHIS
RES Port 0 of CMOS output, P46,P47 *Ports 1,2,3,4(P40P45),5 of CMOS output *ADLC, EROE *Ports 0,1,2,3,4,5 *ADLC, EROE
2.5-6.5
-1 V
4.5-6.5 VDD-1.5 2.5-6.5 VDD-0.4 4.5-6.5 VDD-1 2.5-6.5 VDD-0.5
Port 70 *Ports 0,1,2,3,4,5 *Port 7 *Ports 0,1,2,3,4,5 *Port 7 * RES All pins
Pull-up MOS Tr. resistor Hysteresis Voltage Pin Capacitance
IOL=10mA IOL=1.6mA *IOL=1.0mA *Every pin's IOL1mA IOL=1mA IOL=0.5mA VOH=0.9VDD Output disable
4.5-6.5 4.5-6.5 2.5-6.5 4.5-6.5 2.5-6.5 4.5-6.5 2.5-4.5 2.5-6.5
1.5 0.4 0.4 0.4 0.4 100 200
50 60
70 100 0.1VDD
k V
CP
*f=1MHz *All pins except the measured terminal: VIN=VSS *Ta=25C
2.5-6.5
10
pF
Built-in RC Oscillation Frequency
2.5-6.5
0.3
0.8
2
MHz
No.6722-15/29
LC868364A 4. Pulse Input Conditions at Ta=-30C to +70C, VSS=0V
Parameter High/low Level Pulse Width Symbol tPIH(1) tPIL(1) tPIH(2) tPIL(2) Pins *INT0, INT1 *INT2/T0IN *Refer to figure 7 *INT3/T0IN (The noise rejection clock is selected to 1/1.) *Refer to figure 7 *INT3/T0IN (The noise rejection clock is selected to 1/64.) *Refer to figure 7 * RES *Refer to figure 7 Conditions *Interrupt acceptable *Timer 0-countable *Interrupt acceptable *Timer 0-countable Ratings typ. unit tCYC
VDD[V] 2.5-6.5
min. 1
max.
2.5-6.5
2
tPIH(3) tPIL(3)
*Interrupt acceptable *Timer 0-countable
2.5-6.5
128
tPIL(4)
Reset acceptable
2.5-6.5
200
s
No.6722-16/29
LC868364A 5. Sample Current Consumption Characteristics at Ta=-30C to +70C, VSS=0V The sample current consumption characteristics are the measurement result of Sanyo provided evaluation board. The currents through the output transistors, the pull-up MOS transistors and the bleeder resistors for the LCD are not included.
Parameter Current Drain During Basic Operation (Note 2) Symbol IDDOP(1) Pins VDD Conditions *FmCF=12MHz by ceramic resonator *FsXtal=32.768kHz by Xtal *System clock: 12MHz *Internal RC oscillation stops. *FmCF=6MHz by ceramic resonator *FsXtal=32.768kHz by Xtal *System clock: 6MHz *Internal RC oscillation stops. *FmCF=3MHz by ceramic resonator *FsXtal=32.768kHz by Xtal *System clock: 3MHz *Internal RC oscillation stops. *FmCF=0Hz (when oscillation stops) *FsXtal=32.768kHz by Xtal *System clock: RC oscillation *FmCF=0Hz (when oscillation stops) *FsXtal=32.768kHz by Xtal *System clock: 32.768kHz *Internal RC oscillation stops. Ratings unit typ. max. 10 25 mA
OCR7 VDD[V] min. 0 4.5-6.5
IDDOP(2)
1
4.5-6.5
10
25
IDDOP(3) IDDOP(4) IDDOP(5) IDDOP(6) IDDOP(7) IDDOP(8) IDDOP(9) IDDOP(10) IDDOP(11) IDDOP(12) IDDOP(13)
0 1 0 0 1 0 1 0 1 0 1
4.5-6.5 2.5-4.5 4.5-6.5 2.5-4.5 5.0 3.0
3 6 1.5 0.7 1.2 0.4 0.8 30 50 10 20
9 15 5 3.4 4.5 2.8 3.6 45 80 20 30
A
OCR7: Bit 7 of the oscillation control register.
No.6722-17/29
LC868364A Ta=-30C to +70C, VSS=0V
Parameter Current Drain in HALT Mode (Note 2) Symbol Pins Conditions *HALT mode *FmCF=12MHz Ceramic resonator oscillation *FsXtal=32.768kHz Crystal oscillation *System clock: 12MHz *Internal RC oscillation stops. *Refer to figure 8. *HALT mode *FmCF=6MHz Ceramic resonator oscillation *FsXtal=32.768kHz Crystal oscillation *System clock: 6MHz *Internal RC oscillation stops. *Refer to figure 8. *HALT mode *FmCF=3MHz Ceramic resonator oscillation *FsXtal=32.768kHz Crystal oscillation *System clock: 3MHz *Internal RC oscillation stops *Refer to figure 8. OCR7 VDD[V] min. 0 5.0 Ratings unit typ. max. 4.0 7.0 mA
IDDHALT(1) VDD
IDDHALT(2)
1
5.0
4.0
7.0
IDDHALT(3) IDDHALT(4) IDDHALT(5)
0 1 0
5.0 3.0
1.5 2.3 0.5
2.6 4.0 0.9
IDDHALT(6) IDDHALT(7) IDDHALT(8) IDDHALT(9)
*HALT mode *FmCF=0Hz (when oscillation stops) *FsXtal=32.768kHz crystal oscillation *System clock: RC oscillation *Refer to figure 8.
0 1 0 1
5.0 3.0
400 600 200 300
1600 2400 1300 1500
A
IDDHALT(10 ) IDDHALT(11 ) IDDHALT(12 ) IDDHALT(13 )
*HALT mode *FmCF=0Hz (when oscillation stops) *FsXtal=32.768kHz crystal oscillation *System clock: 32.768kHz *Internal RC oscillation stops *Refer to figure 8.
0 1 0 1
5.0
20 30
35 50 13 18
3.0
7 10
Current Drain in HOLD Mode (Note 2)
IDDHOLD(1) VDD *HOLD mode *Refer to figure 8. IDDHOLD(2) *Ta50C
4.5-6.5 2.5-4.5
0.05 0.02
30 20
(Note 2) The currents of the output transistors, pull-up MOS transistors, the LCD bleeder resistors and the LCD driver are not included.
No.6722-18/29
LC868364A 6. LCD Voltage and LCD Driver Characteristics at Ta=-30C to +70C, VSS=0V
Parameter VX-Ci Drop Voltage (X: 1 to 5) (i: 1 to 32) VX-Ci Drop Voltage (X: 1 to 5) (i: 1 to 32) VX-Si Drop Voltage (X: 1 to 5) (i: 1 to 32) VX-Si Drop Voltage (X: 1 to 5) (i: 1 to 32) V4 Output Voltage V3 Output Voltage V2 Output Voltage V1 Output Voltage Symbol |VD1| Pins, Conditions *Only a Ci terminal for -15A *LCD display ON *1/5 bias *V5=VLCD=VDD *Only a Ci terminal for +15A *LCD display ON *1/5 bias *V5=VLCD=VDD *Only a Si terminal for -15A *LCD display ON *1/5 bias *V5=VLCD=VDD *Only a Si terminal for +15A *LCD display ON *1/5 bias *V5=VLCD=VDD *LCD clock frequency=0Hz *LCD display ON *1/5 bias *V5=VLCD=VDD *Refer to figure 10 Ratings typ. unit mV
VDD[V] 2.9 5.0
min.
max. 120 200
|VD2|
2.9 5.0
-120 -200
|VD3|
2.9 5.0
120 200
|VD4|
2.9 5.0
-120 -200
VV4 VV3 VV2 VV1
2.9 5.0 2.9 5.0 2.9 5.0 2.9 5.0
0.75VDD 0.80VDD 0.85VDD 0.55VDD 0.60VDD 0.65VDD 0.35VDD 0.40VDD 0.45VDD 0.15VDD 0.20VDD 0.25VDD
V
7. Sample LCD Driver Characteristics at Ta=-30C to +70C, VSS=0V
Parameter
LCD Display Current
Symbol ILCD1 ILCD2
Pins, Conditions *LCD display ON *1/5 bias *VLCD=5V *V1-V5 are open. *Refer to figure 9 *LCD display ON *VLCD=5V *V5=VLCD-0.5V *Refer to figure 11 100k mode 50k mode VCCR=1 VCCR=2 VCCR=4 VCCR=8 VCCR=10H
VDD[V] 2.9 5 2.9 5 2.9 2.9 2.9 2.9 2.9
min. 5 5 10 10 125 62 31 15 8
Ratings typ. 10 10 20 20 250 125 62 31 15
max. 20 20 40 40 500 250 125 62 31
unit A
Contrast Current
ILC1 ILC2 ILC3 ILC4 ILC5
VCCR: LCD contrast control register
No.6722-19/29
LC868364A Recommended Oscillation Circuit and Characteristics The oscillation circuit characteristics in the table below are based on the following conditions: * Recommended circuit parameters are verified by an oscillator manufacturer using a Sanyo provided oscillation evaluation board. * The characteristics are the results of the evaluation with the recommended circuit parameters connected externally. Recommended Ceramic Oscillation Circuit and Characteristics (Ta = -30C to +70C)
Frequency Manufacturer
Oscillator
CSA12.0MTZ CST12.0MTW KBR-12.0M CSA6.00MG CSTS0600MG03 KBR-6.0MSA CSA4.00MG CSTS0400MG03 KBR-4.0MSA CSA3.00MG CST3.00MGW KBR-3.0MS
12MHz
MURATA KYOCERA
6MHz
MURATA KYOCERA
4MHz
MURATA KYOCERA
3MHz
MURATA KYOCERA
Operating Oscillation Recommended Circuit supply Voltage Stabilizing Time Parameter Period (typ.) * Range C1 C2 Rd1 3.3 to 6.5V 0.06ms 30pF 30pF 0k 3.3 to 6.5V (30pF) (30pF) 0k 0.06ms 3.3 to 6.5V 0.04ms 22pF 22pF 0k 2.8 to 6.5V 0.08ms 30pF 30pF 0k 2.4 to 6.5V (15pF) (15pF) 0k 0.04ms 2.4 to 6.5V 33pF 33pF 0k 0.05ms 2.7 to 6.5V 30pF 30pF 0k 0.05ms 2.4 to 6.5V (15pF) (15pF) 0k 0.03ms 2.4 to 6.5V 33pF 33pF 0k 0.04ms 2.4 to 6.5V 0.06ms 30pF 30pF 0k 2.4 to 6.5V (30pF) (30pF) 0k 0.06ms 2.4 to 6.5V 0.05ms 33pF 33pF 0k
Notes
built-in capacitor type
built-in capacitor type
built-in capacitor type
built-in capacitor type
Recommended Crystal Oscillation Circuit and Characteristics (Ta = -30C to +70C)
Frequency Manufacturer Seiko Instruments Seiko Epson Oscillator VT-200 C-002RX/MC-306
Oscillation Recommended Circuit Operating supply Stabilizing Time Parameter Voltage Range Period (typ.) * C3 C4 Rd2 2.2 to 6.5V 12pF 12pF 0.6s 330k 2.2 to 6.5V 0.8s 12pF 12pF 330k
Notes
32.768kHz
* The oscillation stabilizing time period is the time until the oscillation becomes stable after the VDD becomes higher than the minimum operating voltage. Notes: * Since the circuit pattern affects the oscillation frequency, place the oscillation-related parts as close to the oscillation pins as possible with the shortest possible pattern length. * If you use other oscillators herein, we provide no guarantee for the characteristics. The oscillation circuit characteristics may differ by applications. manufacturer with the following notes in your mind.
* *
For further assistance, please contact with the oscillator
Since the oscillation frequency precision is affected by wiring capacity of the application board, etc., adjust the oscillation frequency on the production board. The above oscillation frequency and the operating supply voltage range are based on the operating temperature of -30C to +70C. For the use with the temperature outside of the range herein, or in the applications requiring high reliability such as car products, please consult with oscillator manufacturer.
Since the oscillation circuit characteristics are affected by the noise, wiring capacity, etc., refer to the following notices. * The distance between the clock I/O terminal and external parts should be as short as possible. * The capacitors' VSS should be allocated close to the microcontroller's GND terminal and be away from other GND. * The signal lines with rapid state changes or the signal line with large amplitude such as middle withstand voltage port or LCD driver output should be allocated away from the clock oscillation circuit. * The signal lines with large current should be allocated away from the oscillation circuit.
No.6722-20/29
LC868364A
CF1
CF2 Rd1
XT1
XT2 Rd2
C1
CF
C2
C3
Xtal
C4
Figure 1
Ceramic Oscillation Circuit.
Figure 2
Crystal Oscillation Circuit.
RC1
RC2
Figure 3
RC Oscillation Circuit. (when external RC oscillation is selected)
No.6722-21/29
LC868364A
Power Supply
Reset Time
VDD VDD Limit 0V
RES
RC Oscillation
tmsCF
CF1, CF2
tssXtal
XT1, XT2
Operation Mode
Unstable
Reset
Execution of Instructions
Reset Time and Oscillation Stabilizing Time Period
HOLD Release Signal
Valid
RC Oscillation
tmsCF
CF1, CF2
tssXtal
XT1, XT2
Operation Mode
HOLD
Execution of Instructions
HOLD Release Signal and Oscillation Stabilizing Time Period (OCR6=1 at entering HOLD) tmsCF: tssXtal: Oscillation stabilizing time period when using the ceramic resonator oscillator. Oscillation stabilizing time period when using the Xtal oscillator. Figure 4 Oscillation Stabilizing Time Period.
No.6722-22/29
LC868364A
VDD
RRES
RES CRES
(Note) Determine the CRES, RRES value to generate more than 200s reset time.
Figure 5
Reset Circuit.
0.5VDD VDD tCKH
tCKCY tCKL SCK0 SCK1 tICK SI0 SI1 tCKO SO0, SO1 SB0, SB1 50pF tCKI
1k

Figure 6
Serial Input/Output Test Condition.
tPIL
tPIH
Figure 7
Pulse Input Timing Condition.
No.6722-23/29
LC868364A
VDD A VDD V5 V4 V3 V2 V1 VLCD CF1 CF2 VSS XT1 XT2 VDD V5 V4 V3 V2 V1 VLCD CF1 CF2 VSS XT1 XT2 A 5V OPEN VDD
OPEN
VSS
VSS
Figure 8
Current Consumption Measurement.
Figure 9
LCD Display Current Measurement.
VDD
VDD 5V
VDD V5 V4 V3 V2 V1
VDD
A VDD VLCD V5 V4 V3 V2 V1 CF1 CF2 VSS XT1 XT2 VLCD-0.5V OPEN
VDD VLCD CF1 CF2 VSS XT1
XT2 V
VSS
VSS
Figure 10
Output Voltage of V1-V4 Measurement.
Figure 11
Contrast Current Measurement.
Notes: * Figure 8-11 indicate the measurement circuits when using the internal RC oscillator. * When external RC oscillation is selected, an external circuit needs to be connected to RC1 and RC2 terminals.
No.6722-24/29
LC868364A AC Characteristics at Ta=-30C to +70C, VSS=0V Load capacity: 100pF (Port 0, ADLC, EROE ) Load capacity: 80pF (Output terminals except above) *tCLCL=1tCYC/12
External Program Memory Timing
Parameter ADLC Pulse Width Address Settling Time Address Hold Time ADLC " Control Signal EROE Pulse Width Data Delay Time Data Hold Time EROE " Address in Symbol tLHLL tAVLL tLLAX tLLEL tELEH tELIV tEHIX tEHAV From EROE For EROE For ADLC For ADLC For EROE Pads and Conditions VDD[V] 4.5 to 6.5 2.5 to 6.5 4.5 to 6.5 2.5 to 6.5 4.5 to 6.5 2.5 to 6.5 4.5 to 6.5 2.5 to 6.5 4.5 to 6.5 2.5 to 6.5 4.5 to 6.5 2.5 to 6.5 4.5 to 6.5 2.5 to 6.5 4.5 to 6.5 2.5 to 6.5 Ratings min. max. 2tCLCL-40 2tCLCL-160 tCLCL-40 tCLCL-160 tCLCL-35 tCLCL-140 tCLCL-25 tCLCL-100 3tCLCL-35 3tCLCL-140 3tCLCL-125 3tCLCL-400 0 0 tCLCL-8 tCLCL-32 unit ns
Refer to figure 12.
1 tCYC SCLK tCLCL tCLCL
tLHLL ADLC tLLEL tELEH EROE tELIV tEHAV tLLAX tAVLL tEHIX IR A7-A0
Port 0
A7-A0
Port 2
A15-A8
A15-A8
Figure 12
Timing of the External Program Memory/Data Memory.
No.6722-25/29
LC868364A External Data Memory Timing
Parameter
RD Pulse Width WR Pulse Width
Data Address Hold Time
Symbol tRLRH tWLWH tLLAX
Pads and Conditions
For ADLC (read) For ADLC (write)
Data Delay Time Data Hold Time Data Floating Time
Data Address Setting Time
tRLDV tRHDX tRHDZ tAVLL tLLRL tLLWL
From RD From RD From RD For ADLC For RD For WR For WR
ADLC " Control Signal
Data Settling Time Data in WR =1 Data Hold Time Control Signal " ADLC
tQVWL tQVWH tWHQX tRHLH tWHLH
From WR For RD For WR
VDD[V] 4.5 to 6.5 2.5 to 6.5 4.5 to 6.5 2.5 to 6.5 4.5 to 6.5 2.5 to 6.5 4.5 to 6.5 2.5 to 6.5 4.5 to 6.5 2.5 to 6.5 4.5 to 6.5 2.5 to 6.5 4.5 to 6.5 2.5 to 6.5 4.5 to 6.5 2.5 to 6.5 4.5 to 6.5 2.5 to 6.5 4.5 to 6.5 2.5 to 6.5 4.5 to 6.5 2.5 to 6.5 4.5 to 6.5 2.5 to 6.5 4.5 to 6.5 2.5 to 6.5 4.5 to 6.5 2.5 to 6.5 4.5 to 6.5 2.5 to 6.5
Ratings min. max. 6tCLCL-80 6tCLCL-320 6tCLCL-80 6tCLCL-320 3tCLCL-35 3tCLCL-140 2tCLCL-35 2tCLCL-140 5tCLCL-125 5tCLCL-400 0 0 2tCLCL-70 2tCLCL+70 2tCLCL-280 2tCLCL+280 2tCLCL-40 2tCLCL-160 3tCLCL-50 3tCLCL+50 3tCLCL-200 3tCLCL+200 3tCLCL-50 3tCLCL+50 3tCLCL-200 3tCLCL+200 tCLCL-60 tCLCL-240 7tCLCL-140 7tCLCL-560 tCLCL-50 tCLCL-200 tCLCL-50 tCLCL+50 tCLCL-200 tCLCL+200 tCLCL-50 tCLCL+50 tCLCL-200 tCLCL+200
unit ns
Refer to figure 13.
tCLCL 1 tCYC
SCLK
ADLC
EROE
tLLRL tRLDV
tRLRH
tRHLH
RD
tAVLL tLLAX (at reading) tRHDX DATA tLLWL tWLWH
tRHDZ
Port 0
Z tWHLH
WR
tLLAX (at writing) tQVWL tWHQX
Port 0
A7-A0 tQVWH
Figure 13
Timing of the External RAM.
No.6722-26/29
LC868364A
VDD=3V 10
Oscillation Frequency[MHz]
External Capacity=50pF 100pF
1
220pF 390pF
0.1 1 10
External Resistor (k)
100
VDD=5V 10
Oscillation Frequency[MHz]
External Capacity=50pF
1
390pF
100pF 220pF
0.1 1 10 External Resistor (k) 100
2.0 1.8 Oscillation Frequency[MHz] 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0 1 2 3 4 Voltage (V) 5 6 7
R=10k C=100pF
8
Figure 14
External RC Oscillation Frequency Characteristics. (Ta=25C)
No.6722-27/29
LC868364A
!
Evaluation Sample (ES) Shipping Form: LC868364: chip, Evaluation sample: SQFC144 (shown below) or chip
If you use the ES in the package to design and fabricate an evaluation board, refer to the following pin assignment.
* Pin Assignment of evaluation sample (Package type)
108
P30 P31 P32 P33 P34 P35 P36 P37 P00 P01 P02 P03 P04 P05 P06 P07 P20 P21 P22 P23 P24 P25 P26 P27 NC NC NC NC ADLC
EROE RES
VDD NC P50 P51 P52 P53 P54 P55 P56 P57 P17 P16 P15 P14 P13 P12 P11 P10 P73 P72 P71 P70 P47 P46 P45 P44 P43 P42 P41 P40 VSS NC NC NC NC C1
105 100 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37
XT1 XT2 VSS CF1 CF2
110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144
LC868364A-SQFC144
C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 S48/C17 S47/C18 S46/C19 S45/C20 S44/C21 S43/C22 S42/C23 S41/C24 S40/C25 S39/C26 S38/C27 S37/C28 S36/C29 S35/C30 S34/C31 S33/C32 S32 S31 S30 S29 S28
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
VDD RC2 RC1 VLCD V5 V4 V3 V2 V1 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27
No.6722-28/29
LC868364A memo:
PS No.6722-29/29

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